The present invention relates to a packaging technique for a semiconductor device.
As one of semiconductor devices there is known a power transistor used as a switching element in, for example, a power amplifier circuit or a power supply circuit. As to the power transistor, there have been proposed various structures, which have been produced on a commercial basis. For example, in Japanese Published Unexamined Patent Application No. 2000-223634 (Patent Literature 1) there is disclosed a surface-mounted type power transistor. In the same publication (FIG. 17 and paragraphs [0058] and [0059] in the specification) there also is disclosed a technique wherein a portion of lead terminals bonded to electrodes on a main surface of a semiconductor chip are exposed from an upper surface of a resin housing to decrease the heat resistance of a semiconductor package.
[Patent Literature 1]                Japanese Published Unexamined Patent Application No. 2000-223634        